Eliminating the Last Inch with Power on Package

November 7, 2017

We recently announced our new Power on Package technology that enables manufacturers of CPUs, GPUs and ASICs (XPUs) to place power components either on the substrate of their device (on package) or extremely close to the XPU socket. Eliminating the “last inch” between the regulator and the XPU makes possible the level of higher performance required for today’s most demanding applications.

The Need for Higher XPU Performance

top 500 supercomputers performance trendsThe demand for higher performance computing and communications systems is being driven by applications such as the analysis of big data, video rendering and artificial intelligence (for example in autonomous vehicles). The most powerful High Performance Computing (HPC or Supercomputing) systems are on track to increase performance by a factor of 109 in the period from the mid-1990s to 2020.

This demand for performance drives the development of higher performance XPUs requiring more and more power, while the smaller semiconductor feature sizes as predicted by Moore’s law mean supply voltages have reduced so currents have increased dramatically. Today, high-performance XPUs draw many hundreds of Amperes, and have caused the last inch, (consisting of motherboard copper power planes and interconnects within the XPU socket) to become a limiting factor in XPU performance and total system efficiency.

Why the Last Inch is Such a Problem

Voltage regulators are situated as close to the XPU as possible to minimize impedances which add to power losses and limit current slew rates, directly impacting the power that can be delivered to the processor. The resistance of the motherboard copper traces, socket and XPU pins can total several hundred µΩ. With some XPUs drawing 250A to 400A of average current, and peak currents twice that amount, the I2R power loss is significant, even with the best possible layout.

One approach to overcome this challenge is to increase the number of XPU pins used for power delivery. Every pin allocated to power, however, limits the XPU’s I/O capability.  Yet the need for I/O is increasing as XPU designers add functionality and enhance bandwidth to improve performance. More power pins also increase the complexity of the PCB design, making it harder to achieve optimum performance.

Clearly this situation is not sustainable if engineers are to meet the needs of future high-performance applications. The laws of physics mean that a new approach is needed if we are to avoid the last inch becoming the biggest obstacle to achieving higher performance.

The Power on Package Solution

The concept behind Power on Package  builds on Vicor’s Factorized Power Architecture of a PRM (Pre Regulator Module) regulator feeding a VTM (Voltage Transformation Module) current multiplier by repartitioning the functions to enable a portion of the current multiplier to be mounted either within the XPU package or on the same substrate or PCB.

A single Modular Current Multiplier (MCM) is capable of delivering up to 350A today, with higher current capability coming in the near future. Another significant advantage is the low noise of the MCM, which is critical to the processor’s high bandwidth, low voltage I/O performance. The Modular Current Multiplier Driver (MCD) component can be placed anywhere on the motherboard, increasing design flexibility.

The Benefits of Power on Package

Placing the main power delivery device, the MCM, either inside or near the XPU with regulation and control by another component, the MCD, taking place in a non-critical location is the innovation that enables next generation XPUs to deliver higher performance, without restrictions from the last inch of power distribution. Power on Package typically reduces board resistance by a factor of 10, with a 90% reduction in XPU power pins, adding significant I/O pin count. This new approach to powering next generation XPUs is critical to enabling high-performance computing applications.


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