How “Point of Load”​ VRs are no Longer at the Point of Load for CPUs and GPUs

Point of Load (PoL) was coined to describe a decentralized power architecture scheme where the power regulators are placed (as the name suggests) near the point of load vs all regulated voltage rails being distributed from a single centralized point. This decentralized power and PoL works well for most applications. For higher current devices, like the latest CPUs and GPUs (or XPUs) out there, PoL falls short of being at the load. That is, as voltages have dropped and currents have increased such that the ~1″ or more distance and its related impedance from the output of a VR to the XPU is now limiting performance in many designs. This last inch might as well be termed that last mile due to the challenges it creates with power delivery.

the last inch in processor applicationsThe last inch represents not only current traveling through the PCB but also up through a socket to the XPU. In many server designs we see the resistive losses of this last inch anywhere from 400 μΩ to 900 μΩ. If you consider a 250 A XPU, that represents a 25 W to 56 W in losses. In addition to the power loss, there is also the degradation on transient performance. For that same 250 A XPU, the last mile adds between 100 mV and 225 mV to the transient response. Without the ability to overcome this by adding capacitance next to the XPU, the only recourse is to raise the operating voltage of the XPU, resulting in even more power dissipation. Ironically, optimizing and accounting for this last inch encompasses the majority of time in a server power design.

Moving the VR from the server PCB to inside the XPU socket would eliminate this last inch and enable a “power on package” scheme which provides true PoL power to the XPU. To date, several suppliers have shown examples of power resident within the XPU socket/package or specifically on the XPU substrate within the socket. These designs have shown merit but at the cost of increasing the complexity of the XPU substrate design. These designs have also not been able to demonstrate a dramatically lower current delivery from the motherboard to the socket meaning the last inch is still a critical design aspect to deal with.

At Vicor, we also have to deal with the last inch when working with customer designs. However , the Vicor 48 V Direct-to-CPU solution lends itself to a power on package scheme that eliminates all of the negative effects of this last inch and unlike schemes attempting to adopt a conventional multi-phase VR topology.

benefit of including power products in processor packageThe Vicor 48 V Direct-to-CPU design utilizes two highly integrated power path products (the PRM & VTM) with only the VTM needing to be placed at the point of load. This enables the ~48 V (and low current) output of the PRM to be directed into the XPU package to the VTM and provides the following specific design benefits:

  • Extremely low EMI of the VTM enables close proximity to a XPU
  • Reduction of over 95% of dedicated power pins – due to the higher voltage/ low current delivery from the PRM to VTM
  • Single component level placement (VTM) on the XPU substrate
  • No modification of the substrate needed for magnetic structures or multiple component placement – VTM is self contained

As previously noted, eliminating the last inch:

  • Eliminates the server motherboard resistive losses due to the high current distribution
  • Improves transient performance and dramatically reducing the amount of capacitance as compensation is no longer needed for the last inch

In addition, eliminating the last inch:

  • Enables lower copper weight on the server PCB – creating a cost savings
  • Decreases server board design time – no longer needing to design around the last inch
  • Frees up space around the outside of the XPU socket, enabling better routing and faster performance of high speed signal interfaces to nearby memory or co-processors – due to the reduction in motherboard capacitance and elimination of external VR
  • Frees up space around the outside of the XPU socket enabling motherboard signal routing flexibility around the XPU – due to the reduction in motherboard capacitance and elimination of external VR


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