Powering Highly Capacitive Loads with DC-DC Converters – Part 2

April 21, 2015

Second and final part of the series about powering capacitive loads.

To keep the converter from exceeding its current and power ratings during normal operation, the current control block diagram in Figure 3 can be used to control the re-charge current after a high di/dt event. The circuit monitors the current across a shunt resistor and limits recharge current by actively trimming down the voltage of the converter. The limited voltage differential between the converter and the capacitor will limit the capacitor recharge current to keep the converter within it current and power limits. As the capacitor voltage rises, the converter voltage rises until it reaches its set point.

The current limiting method shown in Figure 3 can be used in conjunction with the pre- charge method in Figure 1 allowing for a faster start up. The pre-charge can charge the capacitor to the minimum trim voltage of the converter and then the converter can fully charge the capacitor with its full current rating. Controlling the rate of rise of the output voltage will control the current charging the capacitor. However, most DC-DC converters have a narrow control or trim range from their nominal set voltage. A typical trim range is +/-10%. There are some manufacturers that have a wider trim range where the converter can be trimmed down to -90% of the nominal set voltage. The lower the voltage trim range, the lower the need for an enable circuit as downstream loads typically have a under voltage lockout close to their operating voltage minimum.

Figure 3 – External current limiting block diagram

Figure 3 – External current limiting block diagram

Once the converter is kept within it limits at start up and during operation, we must now ensure system stability. A large capacitor at the output of the DC-DC converter can degrade the phase margin of the system and cause oscillations. To ensure that the converter is stable there must be a minimum amount of impedance in series with the capacitor. The lead or trace impedance, the FET ESR and the ESR of the capacitor contribute to this impedance. The best way to find the minimum value for this impedance is to use a network analyzer and run a system analysis to determine the phase and gain margin. If a network analyzer isn’t available, a load step can be applied to the system and the converter voltage and current wave forms can be analyzed to ensure that there isn’t excessive ringing which is a sign of poor stability.

Once the voltage loop is stable the current control loop in Figure 3 can be examined for its contribution to the system stability. This current control loop is within the control loop of the DC-DC converter and should have a bandwidth well below the systems loop crossover frequency so the two loops don’t interact. In converter systems where the power train’s compensation network is enclosed within the converter, the converter manufacturer can provide enough information to set a suitable cross over frequency for the current control loop. There are some converter manufactures that give the designer the ability to adjust the power train control loop to optimize the performance for a particular application.

Figure 4 shows a converter with an external control loop. The control loop can be optimized to provide peak system performance. This external control loop can be vital in applications were the power system’s response time in critical for proper system operation. This is the case in a periodic pulsed load application where the converter has to recharge the capacitor before the next power pulse. The system stability should be verified with either a network analyzer or a step load test. Systems that are unstable can have voltage excursions that exceed the power system component ratings and can eventually lead to power system failure.

Figure 4 – Converter with external control loop

Figure 4 – Converter with external control loop


This article was originally published in EDN.



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