Output Line Ripple on Power Factor Corrected AC-DC Power Supply Outputs (Part 5)

This is the fifth in a series of blog posts by Harry Vig, Principal Applications Engineer at Vicor. To go to Output Line Ripple on Power Factor Corrected AC-DC Power Supply Outputs (Part 1) click here.

Three Phase Bulk Capacitor Ripple

In theory, the ripple current of a well-balanced three phase system should be zero. Why? Each output ripple current into the bus should be the square on the input sine wave. Each wave then gets squared, which doubles the frequency and provides the same phase shift, but put into the new frame of reference at double the input frequency, the three phase vectors are still 120 degrees apart at their new reference frequency.

How to simulate this? Use the same model as above, but put three phases in, separated by 120 degrees. For a first view, let’s restore the output current pulses to sine waves with no dead time:

Figure 10 – Three-Phase Model

Since we have three times the input power from the three phases, we need to triple the load, done by adding three load resistors rather than one. The last addition is a zero voltage source between PFM outputs and the load resistors, so we can measure total current from the three output stages.

The outputs show the advantage of a balanced three phase system:

Figure 11 – Balanced Three-Phase System

The total output current is 3*6.9A, a steady DC current of 20.7A. There is no line ripple on the 48V bus due to phasor cancellation.

The phasor diagram on the left shows the three phases of the AC line ripple currents, B1, B2, and B3. They are 120 degrees apart, although they rotate at twice the line frequency, 100Hz in this case.

The diagram on the right shows the sum. It only shows the AC portion, not the DC, but shows why the ripple cancels. The length of the sum vector is zero, shown by the return of the three equal phases to the origin point.

Figure 12 – Phasor Diagram for Balanced Three-Phase System

The DC portion, amplitude 6.9A from each current source, adds without regard to the AC phasors, delivering the DC current to the load.

In a real system, however, phase error and phase imbalance in amplitude will cause ripple current under normal real life operating conditions. As an example, a 10% increase amplitude and 12 degree phase is added to the model by changing the current equation for B1:

Figure 13 – Model with Phase Imbalance and Phase Error

The result is a ripple voltage of 1.43Vpp, and ripple current of 2.14Arms in the bulk cap. Still much better than the single phase situation, with three times the output power.

Figure 14 – Ripple Voltage Caused by Phase Error and Imbalance

The phasor diagram is an easy way to calculate the same result. Phasor B1 has been increased 10% in amplitude and advanced 12 degrees. The resultant sum is shown on the vector diagram below, almost 180 degrees out of phase with B2, the same as in the simulator graph above.

Figure 15 – Phasor Diagram for System with Phase Error and Imbalance

Read part six of this series: A Simple Average Model for Output Current Ripple.

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