My Journey: Rapid Prototyping of a Cell-Based, High Performance, High Power DC-DC Converter (part 2)

In which I scavenge for parts and produce the demo on time.

In the first part of this story I related how it seemed a good idea to create a power array demonstrator combining two “rafts” of different VI Chip parts together for a major project. One raft would be composed of PRM (pre-regulator modules), the other BCMs (Bus Converter Modules).

Having settled on the design concept, I had to address connectivity of the PRM modules. The PR bus is a high-impedance line that delivers 10s of microamps to each slave PRM. I decided to incorporate a buffer on the master PRM’s evaluation test fixture to counteract a potential “bus shift” problem on the PR, or current sharing, line.

When setting up arrays of PRMs, you need to make sure that all the PC (primary control) or enable pins on the PRMs are connected to form a group-enable function to ensure the PRMs turn on together. You can make up a simple three-wire bus by including a SG (signal ground) wire to make a general control signaling bus consisting of the PR, PC and SG lines.

I decided to set Bus Converter Modules (BCMs) ahead of the PRMs in the array as they are to buck the input voltage from 270V to 45V DC. The BCM is a rugged device that closely mimics the ideal, textbook DC-DC transformer action: apply 270V DC across one of these BCMs feeding it 1A, and out the other end comes isolated 45V at 5.76A or more, indicating efficiency of 96% or better. BCMs also parallel together easily to allow you to modular high power systems. Besides attending to the symmetrical bussing of the input and output currents, the only other connections that need to be made between each BCM are PC and SG wires, as a twisted pair, to make another group enable function that ensures the BCMs to start together. With the BCM output voltage 45V bucked down and regulated at 28V DC, a complete regulated converter is easily made.

Whenever arrayed VI Chip devices are used, an important design consideration is preventing the interaction between devices at their interconnected input power ports. A low impedance input power bus allows high frequency switching currents to flow between VI Chip modules. VI Chip devices cannot be synchronized in frequency, so there is a strong possibility that beats will manifest themselves on the output busses of the arrayed devices. This can be a major concern where noise spectra have to be managed carefully, e.g. in a RF application, otherwise they can cause EMI problems. Adding small amounts of inductance in between the voltage source and the individual feeds to the BCMs is the way to cure such beating effects there. It is found that the PRM evaluation test fixtures already have enough inductance in their power input layout that no extra inductance is required.

I decided that the demonstrator would look better with the same number of BCMs as the dozen PRMs earmarked for the array. These 12 BCMs, with their 270W power output power capability, could source up to 3.24 kW to the paralleled PRMs following them.

Armed with my “shopping list”, I emailed factory-based colleagues and was relieved to hear that I would get the six outstanding PRM test fixtures I needed within 3 days. I raided the central apps lab for discrete “necessaries” such as fuses and power inductors. At that point, another need came to light. I would want some cooling across each section of the final power array. I located some 12V miniature fans, capable of providing sufficient airflow, lining up columns of 10 fans vertically across each of the twin stacks, so that all the VI Chips receive sufficient airflow.

Once I’d got all the components I needed, everything was organized for a final day at the bench, integrating all the devices in the demo kit.

I ensured each BCM evaluation test fixture on my test bench worked correctly and then constructed the first of the two stacks needed for the demo unit. Close to hand were large bags of aluminum standoffs, a modicum of solid copper insulated wire, a pair of perf-boards for HV insulation and some other hardware. The thing that took the most time to assemble was not the BCM stack, but the wiring to disperse the HV power feed to each of the BCMs. These ended up with a separate 3A fast-acting fuse and 1.8uH inductor in series with each BCM input feed from the HV input line. The BCM stack was finally set up and ready for full scale testing by 4 pm. After retrieving and setting up the Mosbach load, I had everything up and running by the early evening. Around the array I go with a clamp-meter, to see how well the BCMs were doing with load current-sharing. The results were good!

Encouraged, I measured things up for the 45V bus wiring. Symmetrical bussing involves splaying apart the positive and negative return leads on the assembled array to make sure that currents leaving each of the BCMs’ power ports see the same amount of resistance.

At this point I decided it was time for bed!

The next morning found me poring over the compensation circuitry for the master PRM. The slave units had their compensation circuitry disabled, all destined to respond to the master. The settling time associated with the standard compensation for the master PRM is 200 us.

The clock was ticking.

It was mid-morning Friday by this time and I had the master module configured, with the PR buffer set in place on a small tag board mounting on the master test board. I had taken all the remaining PRM fixtures, slave-configured and had them set in another standoff-spaced stack, with the master PRM set in its mid-span. The control bus wiring was installed next.

The second build and test phase involved setting up the PRM stack, the third involved having both the BCM and PRM stacks aligned and connected up on a Perspex platform (a piece I had ‘rescued’ from the equipment area). With the power source set up to deliver current at 270V DC, it was time to light up the whole array. As the setup was running smoothly, I confidently rustled up an audience from around the lab and the adjacent offices; others dropped by as I showed output ripple voltage and then did a load step test triggering a waveform captured on the oscilloscope. Success! Everything on the power array worked – and it looked as if it could be built using a very small amount of PCB real estate.
The end of my journey was, of course, the customer demo.

With a working prototype, their engineers were quickly convinced of the feasibility of my solution, and were impressed by its small size. This project was a success in many ways: as well as providing a proven solution to a real application, I’d learned a lot, had honed my problem solving skills, and developed a real eye for finding useful material around the labs!

 

david-bourners-towers-of-power

Figure 1 – The Final Demo System

 

Table 1: Basic Input-Output Specification for Power Array

Input Voltage (V DC) Output Voltage (VDC) Output Current (A DC)
270 V 28 V 85 – 93 A

Comments are closed.

Find out more about our Cool-Power Buck Regulators subscribe to vicor newsletter Contact Us

Get Connected