Output Line Ripple on Power Factor Corrected AC-DC Power Supply Outputs (Part 2)

This is the second in a series of blog posts by Harry Vig, Principal Applications Engineer at Vicor. To read the first part, Output Line Ripple on Power Factor Corrected AC-DC Power Supply Outputs (Part 1) click here.

A Simple Average Model for Output Current Ripple

In part one of this series, Line Ripple on the Output Voltage Bus I showed an oscilloscope trace of an output voltage waveform from a Vicor AC-DC converter. Here is the same oscilloscope graph without the switching ripple. The goal is to create a simple average model that creates a similar output ripple, accounting for the period of inactivity when the line voltage is low. This inactivity, where the output bus is still discharging linearly from the constant current load, is responsible for the linear portion of the line ripple that resides predominantly between the cursors.

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Figure 2: Output Current Without Switching Ripple

The model made a few substitutions. In order to better stabilize the output voltage, without a feedback loop like the real converter has, a constant resistance load was substituted. The value of the load resistor was calculated as R1 = Vout2 / Pout, which in our case is (48V)2 / 330W = 6.98Ω.

Next, the output current shape was modified from the standard shape to account for the period without power processing. Normally, since we are drawing input current proportional to the input voltage, the power delivered to the secondary side is proportional to sin(ωt)2=1+sin(2ωt), ignoring the phase difference. While a gating function that turns off the input power would be more accurate, I used an offset with the max function to simulate the interval when the converter was not switching, then scaled the amplitude of the sine wave to normalize the average current during the half cycle to 1A.

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Figure 3: Spice Model for Output Voltage Ripple Simulation

The resulting waveform is multiplied by the average output current, Pout/Vout, 6.875A, to scale the current to that needed to generate 48V across R1. The LTspice simulation schematic is shown above.

The output waveforms have a 2.48ms period marked between the cursors where the output current is under 5% of peak current. While ideally the current should start its transition to zero at the cursor, this case is worse than bench measurements because the current outside the 2.48ms dead time should be higher than this model generates.

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Figure 4: Results of Spice Simulation

The average current sourced by B1 is 6.79A, ripple current of C1 is 5.52ARMS, average output voltage of 47.4V rather than 48V used in calculation, maximum, minimum, and line voltage ripple of 49.28V, 45.56V, and 3.72Vpp respectively.

Oddly enough, I’m short a few volts. If I calculate the loss through the ESR of C1, I discover 1.0W missing. Adding this missing watt to the 330 expected to be delivered, changes the model value of R1 to 6.96V, the current source to 6.9A, the average voltage now rises to 48.1V, with maximum, minimum and line ripple at 50.02V, 46.24V, and 3.78Vpp. This compares to 48.74V mean, 51.19V maximum, 46.18V minimum and 5.01Vpp ripple measured on the bench.

This is as close as I expect for the accuracy of the input variables and the simplifications made.

How much error is introduced by changing the load from constant current on the bench from constant resistance in the model? We’ll examine this question in the next section.

 

Read part three of this series: A Simple Average Model for Output Current Ripple.

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