Synthesis of Input Line Current in Power Factor Correction Control

Last year, Vicor presented a poster session at PCIM Europe in Nuremberg, Germany. Below is the paper from the show.

Vicor will again be attending and presenting at this year’s event. Here’s a link to the conference program PCIM Europe 2013. PCIM Europe 2013 (14-16 May in Nuremburg, Germany).


Power Factor Correction (PFC) control has been addressed in a variety of ways over the last twenty years [1], [2]. Majority of focus has always been on the quality of converter’s control technique, and the result in terms of power factor and input current Total Harmonic Distortion (THD). While the most common converter topology has been the non-isolated boost, the need for isolated, low voltage output products led to the development of single stage, isolated topologies [4], [5]. These approaches are all affected by significant trade-offs in terms of converter elements design, as constraints add up quickly and force less-than-optimal component sizes and ratings. In order to minimize those constraints, research has focused on radical approaches, where some reactive elements are actively modulated [6] and better performance is achieved at the expense of available headroom on power factor and line current THD with respect to IEC standards.

This paper summarizes the results of industrial research efforts aimed at maximizing efficiency and density of an isolated converter used as a front-end PFC; the proposed implementation is enabled by a digital control technique.

2. Current shape for optimal converter design

The idea: to avoid operation where line power available for conversion
is minimal. Every switch-mode power supply presents an efficiency curve that quickly approaches zero when
minimal power is processed. In PFC applications, the overall concept is to present pure resistive behavior with respect to the input line, therefore aiming for sinusoidal input power to the converter. The nature of this task implies a variety of trade offs:

  • Continuous conduction mode (CCM), constant frequency operation enable optimal powertrain design, but operate the converter efficiency curve close to zero at line crossings
  • Discontinuous conduction mode (DCM), variable frequency operations enable better efficiency,but the powertrain and magnetics designs are far from optimal
  • Hybrid approaches (light load boost, hysteretic, etc.) present challenges from an EMC and EMI compliance standpoint.

The proposed technique utilizes an effective current modulation angle (or dead-band) with respect to the line voltage, symmetric around the zero crossing, and based on avoiding the portion of the line cycle not significantly concurring to overall power transfer. Figure 1 shows the relative reduction in power effectively drained from a pure sinusoidal line (resistive load) as function of a symmetric conduction angle imposed on the input current (blue trace). The purple trace shows that, for example, 15 degrees of electrical angle around the zero crossing are worth just 3% of total available power, but this avoids the lower 25% of the entire line voltage operating range. The impact on the converter is not in avoiding processing the mere 3% of power with lower efficiency, but rather in optimizing powertrain, magnetics and modulation timing within a narrower voltage range.

constant current peak and resistive load

Figure 1: converter input power vs. line current symmetric conduction angle, constant current peak and resistive load

Figure 2 shows a block diagram of the proposed technique. The green line emphasizes the powertrain: two primary stage “cells” are magnetically coupled with a single ended secondary stage, while their inputs can be configured either in series or in parallel with respect to the (rectified) power line. This approach enables several benefits, the most notable one being the invariance of efficiency with respect to the input voltage.

block diagram of the considered AC/DC converter

Figure 2: block diagram of the considered AC/DC converter

Controls are shown on the bottom of Figure 2 and consist of a “classic” analog voltage regulation loop which manages the control node of an analog modulator in order to control the converter output voltage. The microcontroller implements the algorithm discussed in this paper: the analog loop reference is actively modulated based on input and output voltage, in order to achieve power factor correction and shape the input current appropriately.

It is important to note that the microcontroller only needs input line frequency and phase information in order to enable the powertrains outside the “dead-band” around line zero-crossing. Although input voltage is sampled at a relatively high rate, line frequency acquisition requires few line cycles. This is a minor task for the digital control, whose resources are mostly devoted to achieve power factor correction and shape the line current as explained in the next paragraph.

The “conduction angle” forced on the line current is responsible for 14% of total harmonic distortion (THD); however, all applicable EMC standards are met, as discussed earlier.

3. Propagation of line voltage harmonics

Classic PFC control relies on direct [1] or indirect [3] measurement of the line voltage, which is used to shape the input current accordingly. In cases where supplied line voltage presents higher harmonics content (typically in heavy industrial environments), the following issue can arise: the current drawn by the input line closely follows the shape of the input line voltage. Any higher harmonic on the voltage is also present in the current, which causes further line drops with the same harmonic content, therefore compounding and worsening the overall power distribution quality. Figures 3 and 4 show typical current waveforms for multiplier-based analog PFC controls with ideal supply voltage and clipped supply voltage. Crossover distortion is also shown, which is the inevitable consequence of energy draw limits of pulse-width modulated converter topologies.

PWM, analog-multiplier PFC rectifier waveforms with ideal sinusoidal line voltage

Figure 3: PWM, analog-multiplier PFC rectifier waveforms with ideal sinusoidal line voltage


PWM, analog-multiplier PFC rectifier waveforms with clipped sinusoidal line voltage

Figure 4: PWM, analog-multiplier PFC rectifier waveforms with clipped sinusoidal line voltage

Active compensators are often used in these cases, in order to meet utility regulations, but add operational costs.

A digital algorithm has therefore been developed, with the objective of obtaining a line current shape that meets all applicable IEC standards, achieves high power factor but does not propagate line voltage harmonics. The technique explained here is based on the following targets:

  • To maintain the ratio between input voltage and input current constant, therefore achieving PFC
  • To maintain the ratio of the input voltage (moving) average and the input current (moving) average constant, in order to reduce (and in some cases even cancel) current harmonic content

Equation 1 summarizes how this is achieved: Vin and Vcn are the instantaneous values of the converter input voltage and the control node voltage (as shown in Figure 2) respectively, while Vin and Vcn are their moving average values. Bold V = moving average


The introduction of the average term effectively causes a phase delay, and affects the power factor by about 1%, but significantly reduces the propagation of line voltage distortion to the converter input current, because higher order harmonics whose period falls within the averaging window will have their amplitude reduced (over several sampling periods) within the modulation algorithm. Figure 5 shows the harmonic content of a 120VRMS sinusoid, clipped to 80% of its amplitude, while Figure 6 shows those harmonics individually in the time domain, with a possible averaging window for the digital control (which helps to visualize how by properly managing sampling rate and window width, higher harmonics are practically canceled).

harmonic content of a 120VRMS sinusoid, clipped to 80% of its amplitude

Figure 5: harmonic content of a 120VRMS sinusoid, clipped to 80% of its amplitude

time domain plot of the harmonics in figure 5, with a possible digital averaging window

Figure 6: time domain plot of the harmonics in figure 5, with a possible digital averaging window

4. Experimental results

The proposed technique has been implemented on a high-density integrated front-end module, shown on Figure 7.

330W, universal AC input, 48V output SELV isolated converter

Figure 7: 330W, universal AC input, 48V output SELV isolated converter

The module, based on Figure 2 architecture, implements both control ideas: dead-band around line zero-crossing and moving average digital multiplier. Table 1 shows the theoretical input line current harmonic content (second column) under line voltage distortion (various “clip” levels, first column) side by side with the experimental measurements on complete converter parts (third column).

comparison of theoretical versus obtained line current THD (THDI) under various line voltage distortion (THDV) conditions

Table 1: comparison of theoretical versus obtained line current THD (THDI) under various line voltage distortion (THDV) conditions


The data show evidence of the following:

1. Avoidance of operation around zero crossing causes an input line current THD of 14%, which is aligned with industry-standard analog multiplier controls. The benefits on the converter density and efficiency are very significant, which validates the idea at the heart of the technique.

2. A digital, moving-average multiplier element for power factor correction reduces the amount of harmonics that, from line voltage, can propagate on the line current, worsening the overall power quality of the utility. Even with heavily distorted line voltage, current THD is stable around 14%.

5. Conclusions

The proposed digital technique for AC rectifiers with power factor correction has been analyzed theoretically and validated experimentally. The implementation is relatively simple, and requires a low-cost microprocessor and an operational amplifier. While all the EMI/EMC standards are met, it significantly improves the overall power quality of the utility line, by reducing the voltage harmonic distortion propagation to line current. Moreover, it enables further optimization on the active and passive converter components.

6. Literature

[1] L. Rossetto, et al., “Control techniques for power factor correction converters “, Proc. PEMC’94, pp.1310 – 1318 , 1994
[2] T. Takahashi, Y. Li.: High frequency partial boost power factor correction control circuit and
method, US Patent 7,148,664, 2006F. Maddaleno, “SMPS Design Notes”, Polytechnic of Turin,
[3] K.M. Smedley, S. Cuk, One-Cycle Control of Switching Converters, IEEE Transactions On Power Electronics, Vol. 10, No. 6, November 1995.
[4] ON Semiconductor, “90 W, universal input, single stage, PFC converter”, Dec. 2003.
[5] L. Huber and M. M. Jovanovic, “AC/DC flyback converter,” U. S. Patent No. 6950319, Sept. 2005
[6] Y. Hu, L. Huber, and M. Jovanović, “Universal-Input Single-Stage PFC Flyback with Variable
Boost Inductance for High-Brightness LED Applications”, Twenty-Fifth Annual IEEE Applied
Power Electronics Conference, Palm Springs, CA, February 21-25, 2010, pp. 203-209

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