As electronic PCBs become more densely packed and supply rail voltages proliferate, delivering the right power to all on-board devices with optimal space and power efficiency becomes essential. This article looks at developments in power distribution architecture and device technology that allows designers to achieve this optimization.
As the electronics industry has developed, some inexorable trends have become apparent. Boards decrease in size and become more densely populated. Supply voltages demanded by on-board IC devices such as CPUs, DSPs, FPGAs, logic and memory have proliferated and there is a tendency towards lower levels such as 1.2 V. Minimization of power demand is paramount, partly for Green considerations but also to avoid problems of heating, reliability and operating costs arising from excess power dissipation.
Design engineers today are aware that, because of these issues, using a centralized power supply is rarely an option. Delivering a multitude of low-voltage feeds across a PCB would be prohibitively inefficient both in terms of board space and, because of I²R losses, electrical power. Different distributed power architectures have appeared over the years to address these problems. Their objective is always the same; to develop each low voltage close to where it is needed, at the point of load (POL), while providing regulation and isolation as well as conversion. The success and ongoing development of these architectures is largely dependent on the devices used in their implementation. These have been generating new design opportunities as new semiconductor, transformer and other technologies become available.
The first move away from a centralized design was into Distributed Power Architecture (DPA) where incoming AC is converted into a DC bus feeding independent, isolated DC – DC converters used to drive the output loads. Although this method generates higher overall efficiency due to single-stage conversion for each output rail, it results in higher costs and takes up significantly more board space. These problems become worse as the number of on-board IC devices and voltage rails grows.
The intermediate bus architecture (IBA) overcomes these limitations by using a different approach. An intermediate bus converter device (IBC) converts the DPA’s high DC voltage of 48 V or higher down to an intermediate level of 8 – 12 V that is adequate to power a number of narrow range non-isolated point of load (niPOL) devices. The IBC also provides isolation. Each niPOL generates the desired regulated output voltage for its own local load. Because the niPOLs are smaller than isolated DC –DC converters, IBA architecture is lower cost and uses less board space that a DPA solution. However it is less power-efficient, because of multiple conversions with both the IBC and niPOLs in the power train. Some of the niPOLs’ size and efficiency advantages are lost.
Advances in device technology mean that IBA compromises can be overcome, sometimes partially and sometimes entirely. Essentially a return to DPA architecture has become possible, using iPOL devices with packaging and footprints approaching those of niPOLs. These iPOLs offer a wide input voltage range, so they can be fed by high DC voltages routed across the PCB to minimize I²R losses. Like the original DC –DC converters, these iPOLs offer isolation, voltage conversion and regulation at the point of load, eliminating the need for an IBC device. To the extent that it’s available, new technology is allowing a revised, more efficient and more compact implementation of the original DPA architecture which, further, is an improvement on IBA.
One beneficiary of this approach would be an automated test equipment (ATE) system where isolation is a key requirement. This application could be satisfied efficiently using an iPOL providing isolation, conversion and regulation at the test head. Communications line cards typically also require galvanic isolation, which could now be provided by iPOLs instead of an IBC.
These iPOL devices now encapsulate magnetics, power semiconductor ICs, MOSFETs and passive components inside a single miniature housing. Suppliers are calling them power-supplies-in-a-package, or PSiPs, if they have an integrated inductor, or power-supplies-on-a-chip (PwrSOC) without an inductor. Although these devices represent progress towards ‘ideal’ iPOLs, design and construction of an iPOL with a niPOL-like form factor creates many challenges and added complexities. Their development requires attention to the controller technology, an isolated transformer integrated within the package, MOSFETs and packaging.
Accomplishing such a task requires system-level understanding with the ability to optimize the balance between size, power density, packaging, thermal management and the integrated power-supply topology that works optimally with the semiconductor switching controller. This expertise typically requires a blend of traditional brick design and advanced IC design technologies. Traditional brick designs have reduced open-frame or brick-type supply footprints, but not many have achieved the density and IC-like packaging required for an ideal iPOL. Packaging advances for iPOLs have lagged those of niPOLs.
For example half-, quarter- and eighth-brick sizes have been cut to a sixteenth-brick form factor. Yet this is still two to three times larger than a high-performance semiconductor IC-like package used for niPOL devices. Meanwhile, at IC level, there is only limited evidence of integrated isolation transformers of any significant power. Yet iPOLs do exist and are improving continuously to deliver increasing performance and/or power density. Like niPOLs, iPOLs are expected to continue in their development until they are implemented in semiconductor packages, further increasing their penetration into power system designs.
As this technology develops, designers are expected to take a mixed approach comprising DPA and IBA attributes and using IBCs, niPOLs and iPOLs in combinations optimized for their particular application. This will make the best use of the technology available at any point in time to achieve the greatest flexibility, power density and efficiency currently available.