Background to Factorized Power Architecture

November 25, 2011

Supplying power to early electronics systems was relatively straightforward and could typically be accomplished with a single silver box AC-DC supply. However as system performance, power density and load voltage proliferation steadily increased, more sophisticated power systems architectures became necessary. This article looks at this evolution and introduces Factorized Power Architecture, which allows designers to meet the challenges of today’s high-performance electronics.

Some History and Some Problems

In the beginning, there was 5 V, and it was good.

In the mid Eighties you could build a 19” VMEbus system with several MC68000 processor boards, and some I/O boards as well – and drive them all from a single silver box power supply. If you were lucky this unit had Sense inputs, so you could use feedback to compensate for the voltage drop to the load. OK, there was ±12 V as well, but this was for the communications chips. The real work was being done at 5 V. However the MC68000s were taking mW, not tens ofWatts. Power was transmitted via the backplane, through the DIN 41612 connector pins and across the PCB. This was a centralised power architecture, or CPA.

At these levels cooling wasn’t unduly challenging, and in that period nobody was worried about energy costs or being Green.

Over time, systems have inexorably become faster, more powerful and more compact. Whereas a 20 MHz MC68000 processor dissipated 380 mW, an Intel Itanium 2 server CPU can run at 1.1 GHz with a thermal design power of 260 W. Meanwhile, chip geometries, and therefore voltages have reduced, and voltage rails have proliferated. Also supply rail voltages have gone up – a backplane can typically carry 48 Vdc, compared with the earlier VMEbus 5 V supply. So, designers have to convert from higher source voltages to lower load voltages demanding much higher currents within a more densely populated environment. Efficiency, I²R losses and thermal management have become critical issues. The problems confronting power systems designers as systems’ speed, power and density continue to increase can be summarised as below:

  • Need to supply many low voltages, leading to a proliferation of converters increasing cost and board space demand
  • With very low load voltages – now possibly below 1 V – currents must be correspondingly high, so:
    • Need to derive these low voltage high current supplies close to the POL to avoid unsustainable I²R losses across the PCB or unacceptable trace widths
    • If the system DC rail is 48 V, high duty cycle losses will be sustained in a traditional DC – DC converter due to the wide voltage differentia
  • Microprocessors demand fast step changes in power so board real estate must be expended on capacitors to store readily available energy
  • Space and expense must also be devoted to filters to protect the load from converter noise and harmonics
  • Efficiency and heat dissipation become critical issues

Distributed Power Architecture

Electronics power suppliers have long recognised these problems. One of the earliest responses was the introduction of distributed power architecture (DPA), in which the Silver Box AC-DC power supply was used to serve DC-DC converters distributed near the system’s points of load (POL), typically using an intermediate DC voltage such as 48 V. The AC-DC supply handled rectification, regulation, isolation, noise suppression and power factor correction. The DC-DC converters, implemented using high density bricks, each provided an isolated output voltage at a level suitable for the load they were serving. Compared with the CPA approach, DPA reduced the I²R losses associated with transmitting low voltage around the system and improved dynamic response. It also moved heat generation away from a single source, greatly reducing or eliminating the need for heat sinks or high velocity airflow. Elimination of hotspots improved system reliability.

DPA, however, increased costs and board space consumption because each POL brick had to provide every DC-DC function – isolation, regulation, transformation, EMI filtering and input protection. This problem grew steadily as onboard voltage requirements proliferated. Additionally, as devices continually became faster, their transient response requirements exceeded the capabilities of typical DPA brick topologies.

Furthermore, if a single DC-DC converter could not provide adequate power or fault tolerance for a particular output voltage, multiple DC-DC converters had to be paralleled, creating additional complexity because remote sense leads were required from each paralleled converter to a single, common point, and additional circuitry was needed within each paralleled converter to force power sharing among the units.

Intermediate Bus Architecture

The next evolutionary step in power systems architecture, referred to as Intermediate Bus Architecture (IBA), addressed the problem of load voltage proliferation, by placing inexpensive, non-isolated buck converters at the POL. IBA  was the first to separate the DC-DC functions of isolation, transformation and regulation into two devices – the Intermediate Bus Converter (IBC), which provides isolation and transformation to an intermediate voltage, and the non-isolated Point of Load (niPOL) converter, which provides final transformation to the load’s voltage requirement as well as regulation. Because the niPOLs reduce costs by foregoing isolation, IBA architectures can offer cost-effective solutions. However the niPOLs’ lower costs are also partly due to their limited voltage transformation ratio, which means IBCs must have lower output voltages – typically 12 V – and be closely located to avoid I²R losses across

the PCB. The niPOLs’ lack of isolation makes overvoltage-sensitive loads vulnerable to serious faults and the entire system to ground loop problems. The niPOLs’ ability to respond to dynamic loads is also limited by inductive inertia.

Factorized Power Architecture – concept

The most recent step in power systems evolution is Factorized Power Architecture (FPA) which allows designers to respond better to today’s power systems challenges for two reasons:

  • It uses new, superior electronic converter technology
  • It deploys it in an efficient, ‘Factorized’ topology

Let’s look at the factorization issue first, then examine what it is that’s being factorized!

Supposing you were asked to factorize the expression x² + x, you’d soon (probably) come up with the answer x(x+1). One entity has been factorized into two factors. Each factor is more accessible for management and manipulation.

How does this apply to FPA? We can see how by looking more closely at the DC – DC converter function, and seeing that it actually comprises three sub-functions:

  • Voltage transformation (Converting a voltage from one level to another)
  • Voltage regulation (Controlling the converter output voltage to a target value even when the input voltage varies
  • Isolation

These three sub-functions are traditionally performed within a single unit – the DC – DC converter. However if we factorize this converter out into two separate components, perhaps these components can become more effective as each can focus solely on its specialised role.

Factorized Power Architecture does exactly this – it takes the DC – DC conversion function and factorizes it into two complementary components, implemented within the V·I Chip and VI BRICK families as the Pre-Regulator Module (PRM) and the Voltage Transformation Module (VTM). These two devices work in partnership with one another, each fulfilling its specialised role efficiently to add up to the complete DC – DC conversion function.

The PRM supplies a regulated output voltage, or ‘factorized bus’ from an unregulated input source. This bus feeds one or more VTMs which transform the factorized bus voltage to the level needed by their load, while providing isolation as well. So, a PRM+VTM pair provides the full, regulated, isolated DC – DC converter function. A closer look at their architectures will show why they eliminate the problems previously identified.

Factorized Power Architecture – components

To summarise, a Factorized Power Architecture implementation using V·I Chip or VI BRICK PRM and VTM modules provides complete DC-DC converter functionality – regulation, transformation and isolation – together with the following additional benefits:

  • The VTM and PRM modules each have an efficiency greater than 95%, so thermal management is greatly simplified.
  • An FPA implementation can accept an unregulated 48 V input, and convert it to low voltage high current outputs at the points of load.
  • Chips are small and cost effective, and can be mounted close to the POL with minimal board space loss.
  • Diverse and distributed load voltages can be supplied using multiple VTMs connected to a single PRM, further reducing demand for board space.
  • VI BRICK VTMs have a power density of up to 390 W/in³, can deliver up to 100 A, and can be paralleled if more power is required.
  • With a transient response of ten times better than previously available, the need for energy storage capacitors is sharply reduced with significant savings in cost and board real estate. Also, capacitors can be connected upstream of the VTM, where significantly less capacitance is required to store the same amount of energy; the precise ratio depends on the K factor of the VTM. This benefit arises from the VTM’s ability to process power through the SAC power train rather than being a slave to a slow control loop. This in turn means it can deliver power in just nanoseconds since the control loop for the regulation is handled by the PRN.
  • With fixed frequency operation, and no harmonics, filters can be smaller and cheaper.



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