Optimising Processing Real Estate

October 10, 2007

The drive to create metadata processing server systems plus the parallel push for increased port density and triple-play (voice/video/internet) traffic handling in telecommunication systems places greater demands on power management architectures.

The problem: inefficient power architectures

Traditional designs using AC to 12 Vdc Silver Box followed by 12 V to 1.x Vsynch buck have run aground in terms of system power density and efficiency due to a combination of distribution bus losses and fundamental restrictions in topology performance as processor voltages reach sub-volt levels. Higher voltage (48 V or 350/380 V) bus voltages reduce distribution losses, but usually mean the addition of an extra stage or stages to get down to the processor voltages, which add size and may lower conversion efficiencies.

A new approach is necessary to optimise processing real estate while minimising the area used for power delivery in next generation systems.

The Solution: Factorized Power Architecture (FPA)

Follow this link to read the full white paper on this topic, Enabling Next Generation High Density Power Conversion, which was presented at the IBM Symposium.

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